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features ? ee programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and 4,19 4,304 x 1-bit serial memories d esigned to store configuration programs for field programmable gate arrays (fpgas) supports both 3.3v and 5.0v operating voltage applications in-system programmable (isp) via two-wire bus simple interface to sram fpgas compatible with atmel at6000, at40k and at94k devices, altera ? flex ? , apex ? devices, orca ? , xilinx ? xc3000, xc4000, xc5200, spartan ? , virtex ? fpgas cascadable read-back to supp ort additional configurations or higher-density arrays very low-power cmos eeprom process programmable reset polarity available in 6 mm x 6 mm x 1 mm 8-lead la p (pin-compatible with 8-lead soic/voic packages), 8-lead pdip, 8-lead soic, 20-l ead plcc, 20-lead soic, 44-lead plcc and 44-lead tqfp packages emulation of atmel?s at24cxxx serial eeproms low-power standby mode high-reliability ? endurance: 100,000 write cycles ? data retention: 90 years for industrial parts (at 85 c) and 190 years for commercial parts (at 70 c) green (pb/halide-free/rohs compli ant) package options available 1. description the at17lv series fpga configuration eeproms (configurators) provide an easy- to-use, cost-effective configuration memory for field programmable gate arrays. the at17lv series device is packaged in the 8-lead lap, 8-lead pdip, 8-lead soic, 20- lead plcc, 20-lead soic, 44-lead plcc and 44-lead tqfp, see table 1-1 . the at17lv series configurators uses a simple serial-access procedure to configure one or more fpga devices. the user can select the polarity of the reset function by pro- gramming four eeprom bytes. these dev ices also support a write-protection mechanism within its programming mode. the at17lv series configurators can be programmed with industry-standard pro- grammers, atmel?s atdh2200e programming kit or atmel?s atdh2225 isp cable. fpga configuration eeprom memory at17lv65 at17lv128 at17lv256 at17lv512 at17lv010 at17lv002 at17lv040 3.3v and 5v system support 2321h?cnfg?03/06
2 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 notes: 1. the 8-lead lap package has the same footpr int as the 8-lead soic. since an 8-lead soic package is not available for the at17lv512/010/002 devices, it is possible to use an 8-lead lap package instead. 2. the pinout for the at17lv65/128/256 device s is not pin-for-pin compatible with the at17lv512/010/002 devices. 3. refer to the at17fxxx datasheet, available on the atmel web site. 2. pin configuration figure 2-1. 8-lead lap figure 2-2. 8-lead soic figure 2-3. 8-lead pdip table 1-1. at17lv series packages package at17lv65/ at17lv128/ at17lv256 at17lv512/ at17lv010 at17lv002 at17lv040 8-lead lap yes yes yes (3) 8-lead pdip yes yes ? ? 8-lead soic yes use 8-lead lap (1) use 8-lead lap (1) (3) 20-lead plcc yes yes yes ? 20-lead soic yes (2) ye s (2) ye s (2) ? 44-lead plcc ? ? yes yes 44-lead tqfp ? ? yes yes 8 7 6 5 1 2 3 4 data clk (wp (1) ) reset/oe ce vcc ser_en ceo (a2) gnd 1 2 3 4 8 7 6 5 data clk (wp (1) ) reset/oe ce vcc ser_en ceo (a2) gnd 1 2 3 4 8 7 6 5 data clk (wp (1) ) reset/oe ce vcc ser_en ceo (a2) gnd
3 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 figure 2-4. 20-lead plcc notes: 1. this pin is only available on at17lv65/128/256 devices. 2. this pin is only available on at17lv512/010/002 devices. 3. the ceo feature is not available on the at17lv65 device. figure 2-5. 20-lead soic (1) note: 1. this pinout only applies to at17lv65/128/256 devices. 4 5 6 7 8 18 17 16 15 14 clk (wp1 (2) ) nc (wp (1) ) reset/oe (wp2 (2) ) nc ce nc ser_en nc nc (ready (2) ) ceo (a2) 3 2 1 20 19 9 10 11 12 13 nc gnd nc nc nc nc data nc vcc nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc data nc clk nc reset/oe nc ce nc gnd vcc nc nc ser_en nc nc ceo (a2) nc nc nc
4 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 figure 2-6. 20-lead soic (1) notes: 1. this pinout only applies to at17lv512/010/002 devices. 2. the ceo feature is not available on the at17lv65 device. figure 2-7. 44 plcc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 data nc clk nc nc nc nc reset/oe nc ce vcc nc ser_en nc nc nc nc ceo nc gnd 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 nc reset/oe nc ce nc nc gnd nc nc ceo/a2 nc nc clk nc nc data nc vcc nc nc ser_en nc (wp1 (1) ) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ready
5 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 figure 2-8. 44 tqfp note: 1. this pin is only available on at17lv002 devices. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 nc reset/oe nc ce nc nc gnd nc nc ceo(a2) nc nc clk nc nc data nc vcc nc nc ser_en nc nc nc nc nc nc nc (wp1 (1) ) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ready
6 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 figure 2-9. block diagram notes: 1. this pin is only available on at17lv65/128/256 devices. 2. this pin is only available on at17lv512/010/002 devices. 3. the ceo feature is not available on the at17lv65 device. power on reset ser_en wp1 (2) wp2 (2) (1) ready (2)
7 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 3. device description the control signals for th e configuration eeprom (ce , reset/oe and cclk) interface directly with the fpga device control signals. all fpga devices can control the entire configuration pro- cess and retrieve data from the configuration eeprom without requiring an external intelligent controller. the configuration eeprom reset/oe and ce pins control the tri-state buffer on the data output pin and enable the address counter. when reset/oe is driven high, the configuration eeprom resets its address counter and tri-states its data pin. the ce pin also controls the output of the at17lv series configurator. if ce is held high a fter the reset/oe reset pulse, the counter is disabled and the data output pin is tri-stated. when oe is subsequently driven low, the counter and the data outp ut pin are enabled. when reset/oe is driven high again, the address counter is reset and the data output pin is tri-stated, regardless of the state of ce . when the configurator has driven out all of its data and ceo is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. this is the default setting for the device. since almost all fp gas use reset low and oe high, this document will describe reset /oe. note: 1. the ceo feature is not available on the at17lv65 device. 4. pin description name i/o at17lv65/ at17lv128/ at17lv256 at17lv512/ at17lv010 at17lv002 at17lv040 8 dip/ lap/ soic 20 plcc 20 soic 8 dip/ lap 20 plcc 20 soic 8 dip/ lap/ soic 20 plcc 20 soic 44 plcc 44 tqfp 44 plcc 44 tqfp datai/o122121121240240 clki244243243543543 wp1i????5??5????? reset/ o e i36636836819131913 wp2i ?7??7????? ce i 4 8 8 4 8 10 4 8 10 21 15 21 15 gnd 51010510115101124182418 ceo o 61414614 13 614 13 27 21 27 21 a2 i ? ? readyo????15??15?29232923 ser_en i71717717187171841354135 v cc 82020820208202044384438
8 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 4.1 data three-state data output for configuration. open-collector bi-directional pin for programming. 4.2 clk clock input. used to increment the internal address and bit counter for reading and programming. 4.3 wp1 write protect (1). used to protect portio ns of memory during programming. disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. this pin is only ava ilable on at17lv512/010/002 devices. 4.4 reset/oe output enable (active high) and reset (active low) when ser_en is high. a low level on reset /oe resets both the address and bit counters. a high level (with ce low) enables the data output driver. the logic polarity of this input is programmable as either reset/oe or reset /oe. for most applications, reset should be programmed active low. this document describes the pin as reset /oe . 4.5 wp write protect (wp) input (when ce is low) during programming only (ser_en low) . when wp is low, the entire memory can be written. when wp is enabled (high), the lowest block of the memory cannot be written. this pin is only available on at17lv65/128/256 devices. 4.6 wp2 write protect (2). used to protect portio ns of memory during programming. disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. this pin is only available on at17lv512/010 devices. 4.7 ce chip enable input (active low). a low level (wit h oe high) allows clk to increment the address counter and enables the data output driver. a high level on ce disables both the address and bit counters and forces the device into a low-power standby mode. note that this pin will not enable/disable the device in the two-wire serial programming mode (ser_en low). 4.8 gnd ground pin. a 0.2 f decoupling capacitor between v cc and gnd is recommended. 4.9 ceo chip enable output (active low). this output goes low when the address counter has reached its maximum value. in a daisy chain of at17lv series devices, the ceo pin of one device must be connected to the ce input of the next device in the chai n. it will stay low as long as ce is low and oe is high. it will then follow ce until oe goes low; thereafter, ceo will stay high until the entire eeprom is read again. this ceo feature is not available on the at17lv65 device.
9 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 4.10 a2 device selection input, a2. this is used to enable (or select) the device during programming (i.e., when ser_en is low). a2 has an internal pull-down resistor. 4.11 ready open collector reset state indicator. driven low during power-up reset, released when power-up is complete. it is recommended to use a 4.7 k ? pull-up resistor when this pin is used. 4.12 ser_en serial enable must be held high during fp ga loading operations. bringing ser_en low enables the two-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . 4.13 v cc 3.3v (10%) and 5.0v (5% commercial, 10% industrial) power supply pin. 5. fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configuration pro- gram. the program is loaded either automatically upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the config- uration program from an external memory. th e at17lv serial configuration eeprom has been designed for compatibility wi th the master serial mode. this document discusses the atmel at40k, at40kal and at94kal applications as well as xil- inx applications. 6. control of configuration most connections between the fpga device a nd the at17lv serial eeprom are simple and self-explanatory. the data output of the at17lv series configurator drives din of the fpga devices. the master fpga cclk output drives the clk input of the at17lv series configurator. the ceo output of any at17lv series configurator drives the ce input of the next configurator in a casc aded chain of eeproms. ser_en must be connected to v cc (except during isp). the ready (1) pin is available as an open-collector indicator of the device?s reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. note: 1. this pin is not available for the at17lv65/128/256 devices.
10 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 7. cascading serial configuration eeproms for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configuration memories, cascaded configurators provide additional memory. after the last bit from the first configurator is read, the clock signal to the configurator asserts its ceo output low and disables its data line driver. the second configurator recognizes the low level on its ce input and enables its data output. after configuration is complete, the address counters of all cascaded configurators are reset if the reset /oe on each configurator is driven to its active (low) level. if the address counters ar e not to be reset upon co mpletion, then the reset /oe input can be tied to its inactive (high) level. the at17lv65 devices do not have the ceo feature to perform cascaded configurations. 8. at17lv series reset polarity the at17lv series configurator allows the user to program the reset polarity as either reset/oe or reset /oe. this feature is supported by industry-standard programmer algorithms. 9. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be pro- grammed by the two-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated inside the chip. 10. standby mode the at17lv series configurators enter a low-power standby mode whenever ce is asserted high. in this mode, the at17lv65/128/256 configurator consumes less than 50 a of current at 3.3v (100 a for the at17lv512/010 and 200 a for the at17lv002/040). the output remains in a high-impedance state regardless of the state of the oe input.
11 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 11. absolute maximum ratings* operating temperature.................................... -40 c to +85 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not imp lied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +7.0v maximum soldering temp. (10 sec. @ 1/16 in.).............260 c esd (r zap = 1.5k, c zap = 100 pf)................................. 2000v 12. operating conditions symbol description 3.3v 5v units min max min max v cc commercial supply voltage relative to gnd -0 c to +70 c 3.0 3.6 4.75 5.25 v industrial supply voltage relative to gnd -40 c to +85 c 3.03.64.55.5v
12 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 13. dc characteristics v cc = 3.3v 10% symbol description at17lv65/ at17lv128/ at17lv256 at17lv512/ at17lv010 at17lv002/ at17lv040 units min max min max min max v ih high-level input voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il low-level input voltage 0 0.8 0 0.8 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 2.4 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 0.4 v v oh high-level output voltage (i oh = -2 ma) industrial 2.4 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 0.4 v i cca supply current, active mode 5 5 5 ma i l input or output leakage current (v in = v cc or gnd) -10 10 -10 10 -10 10 a i ccs supply current, standby mode commercial 50 100 150 a industrial 100 100 150 a 14. dc characteristics v cc = 5v 5% commercial; v cc = 5v 10% industrial symbol description at17lv65/ at17lv128/ at17lv256 at17lv512/ at17lv010 at17lv002/ at17lv040 units min max min max min max v ih high-level input voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il low-level input voltage 0 0.8 0 0.8 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 3.7 3.86 3.86 v v ol low-level output voltage (i ol = +3 ma) 0.32 0.32 0.32 v v oh high-level output voltage (i oh = -2 ma) industrial 3.6 3.76 3.76 v v ol low-level output voltage (i ol = +3 ma) 0.37 0.37 0.37 v i cca supply current, active mode 10 10 10 ma i l input or output leakage current (v in = v cc or gnd) -10 10 -10 10 -10 10 a i ccs supply current, standby mode commercial 75 200 350 a industrial 150 200 350 a
13 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 15. ac waveforms 16. ac waveforms when cascading ce reset/oe clk data t sce t lc t hc t cac t oe t ce t oh t hoe t sce t hce t df t oh ce reset/oe clk data ceo t cdf t ock t oce t oce t ooe last bit first bit
14 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. 17. ac characteristics v cc = 3.3v 10% symbol description at17lv65/128/256 at17lv512/010/002/040 units commercial industrial commercial industrial min max min max min max min max t oe (1) oe to data delay 50 55 50 55 ns t ce (1) ce to data delay 60605560ns t cac (1) clk to data delay 75 80 55 60 ns t oh data hold from ce , oe, or clk 0000 ns t df (2) ce or oe to data float delay 55 55 50 50 ns t lc clk low time 25 25 25 25 ns t hc clk high time 25 25 25 25 ns t sce ce setup time to clk (to guarantee proper counting) 35 60 30 35 ns t hce ce hold time from clk (to guarantee proper counting) 0000 ns t hoe oe high time (guarantees counter is reset) 25 25 25 25 ns f max maximum clock frequency 10 10 15 10 mhz 18. ac characteristics when cascading v cc = 3.3v 10% symbol description at17lv65/128/256 at17lv512/010/002/040 units commercial industrial commercial industrial min max min max min max min max t cdf (2) clk to data float delay 60 60 50 50 ns t ock (1) clk to ceo delay 55 60 50 55 ns t oce (1) ce to ceo delay 55 60 35 40 ns t ooe (1) reset /oe to ceo delay 40 45 35 35 ns f max maximum clock frequency 8 8 12.5 10 mhz
15 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. 19. ac characteristics v cc = 5v 5% commercial; v cc = 5v 10% industrial symbol description at17lv65/128/256 at17lv512/010/002/040 units commercial industrial commercial industrial min max min max min max min max t oe (1) oe to data delay 30 35 30 35 ns t ce (1) ce to data delay 45 45 45 45 ns t cac (1) clk to data delay 50 55 50 50 ns t oh data hold from ce , oe, or clk 0 0 0 0 ns t df (2) ce or oe to data float delay 50 50 50 50 ns t lc clk low time 20 20 20 20 ns t hc clk high time 20 20 20 20 ns t sce ce setup time to clk (to guarantee proper counting) 35 40 20 25 ns t hce ce hold time from clk (to guarantee proper counting) 0000 ns t hoe oe high time (guarantees counter is reset) 20 20 20 20 ns f max maximum clock frequency 12.5 12.5 15 15 mhz 20. ac characteristics when cascading v cc = 5v 5% commercial; v cc = 5v 10% industrial symbol description at17lv65/128/256 at17lv512/010/002/040 units commercial industrial commercial industrial min max min max min max min max t cdf (2) clk to data float delay 50 50 50 50 ns t ock (1) clk to ceo delay 35403540ns t oce (1) ce to ceo delay 35353535ns t ooe (1) reset /oe to ceo delay 30353030ns f max maximum clock frequency 10 10 12.5 12.5 mhz
16 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 notes: 1. for more information refer to the ?thermal characteri stics of atmel?s packages?, available on the atmel web site. 2. airflow = 0 ft/min. 21. thermal resistance coefficients (1) package type at17lv65/ at17lv128/ at17lv256 at17lv512/ at17lv010 at17lv002 at17lv040 8cn 4 leadless array package (lap) jc [ c/w] 45 45 45 ? ja [ c/w] (2) 115.71 135.71 159.60 ? 8p3 plastic dual inline package (pdip) jc [ c/w] 37 37 ? ? ja [ c/w] (2) 107 107 ? ? 8s1 plastic gull wing small outline (soic) jc [ c/w]45??? ja [ c/w] (2) 150 ? ? ? 20j plastic leaded chip carrier (plcc) jc [ c/w] 35 35 35 ? ja [ c/w] (2) 90 90 90 ? 20s2 plastic gull wing small outline (soic) jc [ c/w] ? ja [ c/w] (2) ? 44a thin plastic quad flat package (tqfp) jc [ c/w] ? ? 17 17 ja [ c/w] (2) ??6262 44j plastic leaded chip carrier (plcc) jc [ c/w] ? ? 15 15 ja [ c/w] (2) ??5050
17 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 figure 21-1. ordering code package type 8cn4 8-lead, 6 mm x 6 mm x 1 mm, leadless array package (lap) ? pin-compatible with 8-lead soic/void packages 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 20j 20-lead, plastic j-leaded chip carrier (plcc) 20s2 20-lead, 0.300" wide, plastic gull wing small outline (jedec soic) 44a 44-lead, thin (1.0 mm) plastic qu ad flat package carrier (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) vo l t a g e size (bits) special pinouts package te m p e r a t u r e 65 = 65k a = altera 8cn4 c = commercial 128 = 128k blank = xilinx /atmel/ = 8p3 i = industrial 256 = 256k = 8s1 512 = 512k = 20j 010 = 1m = 44a 002 = 2m = 44j 040 = 4m at17lv65a-10pc c p n j s tq bj = 3.0v to 5.5v other = 20s2 u = fully green
18 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 22. ordering information 22.1 standard package options memory size ordering code package operation range 64-kbit (1) at17lv65-10cc 8cn4 commercial (0 c to 70 c) at17lv65-10pc 8p3 at17lv65-10nc 8s1 at17lv65-10jc 20j at17lv65-10sc 20s2 at17lv65-10ci 8cn4 industrial (-40 c to 85 c) at17lv65-10pi 8p3 at17lv65-10ni 8s1 at17lv65-10ji 20j at17lv65-10si 20s2 128-kbit (1) at17lv128-10cc 8cn4 commercial (0 c to 70 c) at17lv128-10pc 8p3 at17lv128-10nc 8s1 at17lv128-10jc 20j at17lv128-10sc 20s2 at17lv128-10ci 8cn4 industrial (-40 c to 85 c) at17lv128-10pi 8p3 at17lv128-10ni 8s1 at17lv128-10ji 20j at17lv128-10si 20s2 256-kbit (1) at17lv256-10cc 8cn4 commercial (0 c to 70 c) at17lv256-10pc 8p3 at17lv256-10nc 8s1 at17lv256-10jc 20j at17lv256-10sc 20s2 at17lv256-10ci 8cn4 industrial (-40 c to 85 c) at17lv256-10pi 8p3 at17lv256-10ni 8s1 at17lv256-10ji 20j at17lv256-10si 20s2 512-kbit (1) at17lv512-10cc 8cn4 commercial (0 c to 70 c) at17lv512-10pc 8p3 at17lv512-10jc 20j at17lv512-10sc 20s2 at17lv512-10ci 8cn4 industrial (-40 c to 85 c) at17lv512-10pi 8p3 at17lv512-10ji 20j at17lv512-10si 20s2
19 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 notes: 1. for operating 5v operating voltage, please re fer to the corresponding ac and dc characteristics. 2. the last-time buy is april 11, 2006 for shaded parts. 3. for the -10cc and -10c i packages, customers may migrate to at17lvxxx-10cu. 1-mbit (1) at17lv010-10cc 8cn4 commercial (0 c to 70 c) at17lv010-10pc 8p3 at17lv010-10jc 20j at17lv010-10sc 20s2 at17lv010-10ci 8cn4 industrial (-40 c to 85 c) at17lv010-10pi 8p3 at17lv010-10ji 20j at17lv010-10si 20s2 2-mbit (1) at17lv002-10cc 8cn4 commercial (0 c to 70 c) at17lv002-10jc 20j at17lv002-10sc 20s2 at17lv002-10tqc 44a at17lv002-10bjc 44j at17lv002-10ci 8cn4 industrial (-40 c to 85 c) at17lv002-10ji 20j at17lv002-10si 20s2 at17lv002-10tqi 44a at17lv002-10bji 44j 4-mbit (1) at17lv040-10tqc at17lv040-10bjc 44a 44j commercial (0 c to 70 c) at17lv040-10tqi at17lv040-10bji 44a 44j industrial (-40 c to 85 c) 22.1 standard package options (continued) memory size ordering code package operation range
20 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 note: 1. for operating 5v operating voltage, please re fer to the corresponding ac and dc characteristics. 22.2 green package options (pb/halide-fr ee/rohs compliant) memory size ordering code package operation range 256-kbit (1) at17lv256-10cu 8cn4 industrial (-40 c to 85 c) at17lv256-10ju 20j at17lv256-10nu 8s1 at17lv256-10pu 8p3 at17lv256-10su 20s2 512-kbit (1) at17lv512-10cu 8cn4 industrial (-40 c to 85 c) at17lv512-10ju 20j 1-mbit (1) at17lv010-10cu 8cn4 industrial (-40 c to 85 c) at17lv010-10ju 20j at17lv010-10pu 8p3 2-mbit (1) at17lv002-10cu 8cn4 industrial (-40 c to 85 c) at17lv002-10ju 20j at17lv002-10su 20s2 at17lv002-10tqu 44a 4-mbit (1) at17lv040-10tqu 44a industrial (-40 c to 85 c)
21 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23. packaging information 23.1 8cn4 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn4 , 8-lead (6 x 6 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn4 11/14/01 pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 d 5.89 5.99 6.09 e 4.89 5.99 6.09 e 1.27 bsc e1 1.10 ref l 0.95 1.00 1.05 1 l1 1.25 1.30 1.35 1 note: 1. metal pad dimensions.
22 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.2 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
23 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.3 8s1 ? soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s 1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimen s ion s (unit of measure = mm) s ymbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances , datums, etc. ? e 1 n top view c e1 e 1 end view a b l a1 a 1 e d side view
24 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.4 20j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
25 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.5 20s2 ? soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s2 , 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 1/9/02 20s2 a l a1 end view side view top view h e b n 1 e a d c common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation ac for additional information. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exc eed 0.15 mm (0.006") per side. 3. dimension "e" does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "l" is the length of the terminal for soldering to a substrate. 5. the lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. a 0.0926 0.1043 a1 0.0040 0.0118 b 0.0130 0.0200 4 c 0.0091 0.0125 d 0.4961 0.5118 1 e 0.2914 0.2992 2 h 0.3940 0.4190 l 0.0160 0.050 3 e 0.050 bsc
26 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.6 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
27 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 23.7 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
28 2321h?cnfg?03/06 at17lv65/128/256/512/010/002/040 24. revision history revision level ? release date history h ? march 2006 added last-time buy for at17lvxxx-10cc and at17lvxxx-10ci.
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